What is it?

The HC11 CPU Core is a fully-synthesizable VHDL implementation of the HC11 CPU. All instructions are currently implemented with the exception of the divide instructions. The GM HC11 CPU Core package includes the synthesizable core, projects, self-checking testbenches and a debugger.

What is the core's performance?

We have synthesised the CPU core for both Xilinx and Altera FPGAs using FPGA Express from Synopsys. The design used 1076 slices and runs at 31MHz on the Xilinx Virtex 400E part. On the Altera APEX 20K100 part, the design ran at 32MHz and used 2142 LEs.

How much does it cost?

The GM HC11 CPU Core package is a free download. You can also redistribute synthesized designs based on this package for commercial or non-commercial use. However, you may not distribute the package any further in source form. For more information, see the license.txt file included in the package.

Where do I get it?

• You may download the VHDL source here.

  The included project files and debugger require VHDL Studio, which may be downloaded here. VHDL Studio is NOT for required for synthesis or normal VHDL simulation.

• New! You may now download Verilog source here courtesy of Alternative System Concepts, Inc. (ASC)

  The Verilog version was automatically generated by ASC's VHDL2Verilog translator.

Updates

• Added proper masking of interrupt via CCR(IBIT).
• Fixed BSR instruction because it retrieved the wrong address for the PC.
• Removed addition in second address of interrupt/reset vector fetch statements (includes SWI/WAI instructions)
• Fixed SWI/WAI operation to:
• Correct final stack pointer setting
• Ensure proper CCR bits are set to prevent interrupt stacking.
• Fixed incorrect TSI/TIS instruction operation. (Last valid value is always located at SP+1.)
• Fixed two problems with MUL
• Incorrect address fetch at end of MUL.
• Incorrect inclusion of carry_in within alu_out assignment for ALU_MUL.
• Added IDIV/FDIV.
• Restructured the cond_op logic section to simplify inclusion of IDIV/FDIV.