Chapter 3 - Data Flow Descriptions

Section 4 - Other Types

In the previous sections all of the signals in the examples have been of the type bit. VHDL provides several other types, some of which are described here. Often times we use several bit signals together to represent a binary number in a design. VHDL provides a mechanism for defining new types which represent a collection of several data items of the same type. These kinds of types are called arrays. There is a predefined array type called bit_vector which represents a collection of bits. The following example demonstrates how the bit_vector type can be used to define a 1-to-4-line demultiplexer.
entity demux is
  port (e: in bit_vector (3 downto 0);     -- enables for each output
	s: in bit_vector (1 downto 0);     -- select signals
	d: out bit_vector (3 downto 0));   -- four output signals
end demux;

architecture rtl of demux is
  signal t : bit_vector(3 downto 0);       -- an internal signal
  t(3)<=s(1) and s(0);
  t(2)<=s(1) and not s(0);
  t(1)<=not s(1) and s(0);
  t(0)<=not s(1) and not s(0);
  d<=e and t;
end rtl;
Comments can be added at the end of a VHDL statement or on a line by itself preceeded by the -- symbol. First notice how the bit_vector is used in the definition of a signal. The definition of s indicates that s is a bit_vector and the (1 downto 0) part specifies that the signal s contains two bits numbered 1 down to 0. Similarly, d and e are arrays of 4 bits numbered from 3 down to 0. Second, notice that signals, such as t, can be declared within an architecture that are not visible from outside this entity. These internal signals are created with signal declarations as the one in the example. They contain the key word signal followed by a list of names of the signals to create, followed by the type of the signals. Third, the architecture refers to the individual bits in t and s by number. The two bits in s are number 1 and 0, so they are referred to as s(1) and s(0). Finally, notice that the last signal assignment demonstrates that operations can be performed on a whole array of data at once. This statement is equivalent to the four following statements.
d(3)<=e(3) and t(3);
d(2)<=e(2) and t(2);
d(1)<=e(1) and t(1);
d(0)<=e(0) and t(0);
Each data item in an array is called an element. The number of elements in a signal of an array type is indicated by the range that follows the type name. The elements are numbered according to the range, and each element is referred to as an individual by number. Operations can be performed on an array as a whole (applying to every element in the array), or they can be performed using individual elements of the array, independent of the others.

When operations are performed on whole vectors, the vectors must have the same number of elements. If they do not, the simulator will report an error and stop the simulation. In an operation between vectors, elements are matched as they are number from left to right. Thus, if a variable v1 has elements 0 to 1 and variable v2 has elements 1 downto 0. Then

would assign v2(1) to v1(0) and v2(0) to v1(1).

Another predefined type is time. This type is used to represent values of time. We have already used constant values of this type in the after clause. Time is an example of a physical type. All values of a physical type have two parts, a number and a unit name. The type time includes the following predefined unit names sec (seconds), ms (milliseconds), us (microseconds), ns (nanoseconds), ps (picoseconds), and fs (femtoseconds). There are several other types predefined in VHDL including types for integers and real numbers. These are mentioned later in the sections related to behavioral descriptions. There are also many capabilities for defining your own types, which is beyond this tutorial but are described in standard VHDL texts.

The previous section is Data Flow Descriptions - The Delay Model.
The next section is Data Flow Descriptions - Other Operators.

Copyright 1995, Green Mountain Computing Systems.
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